Unsloth와 엔비디아, 소비자용 GPU에서 LLM 학습 25% 속도 향상 달성

unsloth Models Blog Unsloth Studio✨ Docs Blog How to Make LLM Training Faster with Unsloth and NVIDIA May 6, 2026 May 6, 2026 Authors: Daniel, Michael, Mathew and Datta, with help from NVIDIA Fine-tuning is one of today's most computationally intensive workloads, and it continues to push hardware to its limits. NVIDIA GPUs are purpose-built for these workloads: they break complex problems into pieces and process them in parallel. Unsloth works across the breadth of NVIDIA GPUs, from local RTX laptops to DGX Spark personal AI supercomputers. To help developers get the most out of their GPUs, Unsloth has teamed up with NVIDIA to eliminate hidden bottlenecks that slow down training. These newly implemented optimizations accelerate GPU training speeds by ~25% when combined. Here is exactly how we did it. When optimizing model training, developers often start with the usual high-impact kernels: matmuls, attention, fused ops, grouped GEMM, and so on. Although those kernels do most of the arithmetic, once the main components are optimized, a different class of bottlenecks emerges. The GPU stalls on metadata-dependent work. The runtime rebuilds identical data structures every iteration, and copy/compute streams execute in sequence when they could instead overlap. By targeting these bottlenecks, Unsloth and NVIDIA collaborated on three improvements: Caching packed-sequence metadata to avoid reconstructing it across layers Using two buffers during gradient checkpointing so activation reloads can overlap with backward compute Making GPT-OSS MoE routing cheaper by grouping tokens once with argsort and bincount The common pattern across these optimizations is simple: do less repeated bookkeeping, and make copy work happen in parallel with useful compute. 1. Caching Packed-Sequence Metadata Suppose we have several short examples: Instead of padding all of them to the same length and wasting compute on padding tokens, we concatenate them into one longer packed sequence: The model still needs to know where each original sequence starts and ends. So, alongside the packed tokens, we carry sequence metadata such as: sequence lengths cumulative sequence offsets ( cu_seqlens ) the maximum sequence length attention structure derived from the three items above This is the key point: for a fixed packed batch, that metadata is the same for every layer. If we write the boundary information for a packed batch as: B = { lengths, cu_seqlens, max_seqlen, mask structure } then every transformer layer in that forward pass consumes the same B . If the model has L layers, rebuilding or re-synchronizing on B once per layer is not new work. It is the same information being reconstructed again and again. In other words, the useful work is: build B once, use it L times. The wasteful version is: build B + build B + ⋯ + build B ( L times) The overhead here is not primarily extra FLOPs. Some of these paths can force device-to-host synchronization, effectively creating a GPU-CPU sync point. Once that happens inside a per-layer path, the overhead recurs at every layer. That is what the packed-sequence caching change reduces. Instead of repeatedly reconstructing packed sequence info, SDPA packed masks, and xFormers block masks, it caches the reusable metadata and the attention-side structures derived from it, per device, for the current packed batch. Those cached structures are then reused across layers. Why this helps Packed training already improves utilization by eliminating padding waste. But if the metadata path keeps forcing synchronization, some of that gain is lost to overhead that has nothing to do with the model's actual learning. Caching helps because it removes repeated coordination work from the hot path. The forward pass benefits the most because that is where the same packed metadata is consumed repeatedly across many layers. Benchmarks On Qwen3-14B QLoRA SFT : forward: +43.3% backward: +5.8% per batch: +14.3% The forward pass sees the biggest benefit because repeated metadata and mask preparation show up most directly there. Backward also improves, but the effect is smaller. The time saved is similar, but the backward pass, especially with gradient checkpointing, takes longer, so the relative gains appear smaller. Now that we know the measured gain, we can ask a simpler question: does that scale make sense? A quick sanity check If we assume each layer is roughly similar, we can model the packed-attention path as: T_uncached ≈ L · ( A + s ) where: L is the number of layers, A is the useful attention-side work per layer, s is the repeated metadata and mask-preparation overhead per layer. With caching, that repeated overhead is paid once for the batch instead of once per layer: T_cached ≈ L · A + s So the saved time is approximately: T_saved ≈ ( L − 1) · s For the packed SDPA path, our microbenchmark on NVIDIA Blackwell GPUs showed that the low-level, host-visible metadata calls were real but small, at about 0.2 ms each. The dominant repeated cost was the packed SDPA mask-construction path itself, which measured about 13.7 ms for a synthetic packed batch with 2048 total packed tokens. For the SDPA backend, a better mental model is: small stream fence + mask rebuild ≈ mask rebuild That lets us do a cleaner consistency check. If one packed-mask rebuild costs m milliseconds, then under a uniform-layer model: T_saved ≈ ( L − 1) · m With m ≈ 13.7 ms, that predicts: 16 layers: (16 - 1) x 13.7 ≈ 206 ms 28 layers: (28 - 1) x 13.7 ≈ 370 ms Smaller packed-sequence runs showed the same pattern: Llama-3.2-1B , 16 layers: about 199 ms saved per step, which is about 11.5% lower end-to-end step time Qwen3-0.6B , 28 layers: about 319 ms saved per step, which is about 14.8% lower end-to-end step time Those percentages are relative to full training step time, so they still include work outside the packed-attention path, such as embeddings, the MLP, the LM head, the loss, and framework overhead. This estimate is intentionally only about the packed-attention side of the block, not the whole transformer layer. It is there only to check that the measured gains are in the right range for the packed SDPA path. 2. Hiding Latency With Double-Buffered Checkpoint Reloads Activation checkpointing is a standard technique for training large models. The idea is to save memory by not keeping every intermediate activation alive through the backward pass. In exchange, we pay for some extra work during backward. That trade-off is usually worth it, especially for larger models. But it raises another systems question: if an activation has been offloaded, how does it get back to the GPU for backward? In Unsloth's smart checkpointing path, activations can be staged in pinned CPU memory and copied back when needed. That saves VRAM, but it can introduce a bottleneck: Copy the activation from CPU to GPU. Wait for the copy to complete. Run backward compute on that activation. Start the next copy. That is a serialization pattern. If one buffer is reused for both copy and compute, the copy stream and the compute stream keep taking turns. Let T_copy be the activation reload time and T_compute be the backward compute time for the current layer. With a single buffer, this part of the step is roughly limited by: T_single ≈ T_copy + T_compute That is the serialized case. We pay for both almost entirely, one after the other. A cleaner way to handle this is to use two buffers. While the backward pass is running on buffer A , the copy stream can preload the next activation into buffer B . Then the roles swap. That creates pipeline overlap, though not perfect overlap. Double buffering does not reduce the amount of math. It hides copy latency behind useful compute. Why this helps This kind of optimization tends to get stronger once the model is large enough that backward compute is substantial, but not so dominant that all copy overhead disappears into noise. For larger models, higher hidden dimensions mean more data movement, so hid