광통신·CPO 공급망 90개사 분석 도구

What is co-packaged optics (CPO)? Co-packaged optics integrates the optical engine — InP laser, silicon photonics chiplet, modulators, and photodetectors — directly into the same package as the switch ASIC or AI accelerator. By eliminating the long electrical traces between a front-panel pluggable transceiver and the switch silicon, CPO reaches 1.6T–6.4T per port at a fraction of the power per bit. As AI accelerator fabrics scale beyond a single rack, CPO becomes the gating technology for optical I/O. The four package layers InP laser die — gallium-indium-phosphide chips that emit continuous-wave or modulated light. Built on InP epitaxial wafers with MOCVD-grown active layers. Hybrid bond interface — direct copper-to-copper and oxide-to-oxide bonding that fuses the InP die to the silicon photonics chiplet at sub-micron alignment. Silicon photonics (SiPh) chiplet — passive and active waveguides, ring modulators, grating couplers, and germanium photodetectors patterned in CMOS-grade silicon-on-insulator. Switch ASIC or accelerator — the digital silicon (Broadcom Tomahawk, NVIDIA Spectrum-X / Quantum-X, custom hyperscaler XPUs) that sits inches from the optics through advanced packaging. Supply-chain chokepoints SOITEC — engineered SOI wafers; functionally no second-source for the SiPh substrate. ASML — EUV lithography for the leading-edge switch ASIC; sole supplier worldwide. Sumitomo Electric and IQE — InP epitaxial wafers; a duopoly with multi-quarter lead times. EV Group — wafer-to-wafer hybrid bonders; the rate-limiting step at the laser-to-SiPh interface. TSMC — CoWoS-S and CoWoS-L advanced packaging for the assembled CPO stack. Lumentum, Coherent, Sivers Photonics — vertically integrated InP and merchant CW/EML laser sources; Sivers is a strategically important non-Asian, non-US foundry. Shin-Etsu and SUMCO — 12-inch silicon wafers feeding the SiPh chiplet. Linde and Air Liquide — helium and ultra-pure rare gases consumed by the EUV light source and III-V MOCVD reactors. Why CPO is replacing pluggable transceivers Pluggable optics push the optical interface to the chassis front panel and accept the power penalty of long, lossy electrical traces back to the switch silicon. At 800G that is uncomfortable; at 1.6T it is untenable. By placing the optics within the same package as the ASIC, CPO eliminates the trace loss, cuts power per bit by roughly half, and unlocks the bandwidth density needed for AI training fabrics with millions of accelerators. Broadcom shipped CPO switches at scale starting in 2025; NVIDIA's Spectrum-X / Quantum-X / Bailly platforms and hyperscaler-custom CPO switches follow in 2026–2027. Author Curated by Leonardo Boquillón , who writes the Leonardo Boquillón Briefs on Substack — weekly analysis of AI semiconductor supply chains, Japanese technology equities, and compute infrastructure.